The present invention relates to a semiconductor device and a manufacturing technology thereof. In particular, the invention pertains to a technology effective when applied to the manufacture of a semiconductor device having a conductive film formed, after a probe test step is performed by bringing a probe needle into contact with a pad, on the pad by plating.
In a probe test step (test step) of a semiconductor device equipped with a semiconductor circuit (for example, LSI), electrical properties are measured by bringing a probe needle (probe) into contact with the surface of a pad formed over a semiconductor wafer. Since this probe needle is made of a hard metal such as W (tungsten) and has a sharp top, it inevitably gives an external damage, as a probe mark, to the surface of a pad made of, for example, Al (aluminum) during the probe test step.
Japanese Patent Laid-Open No. 2007-318014 (Patent Document 1) discloses a technology of carrying out inspection by bringing a probe needle into contact with one of two regions of a pad and forming a bump electrode in the other region having no probe mark.